CPU PipelineCycle 0CPI —DATA HAZBRANCH FLUSHLOAD-USE
Instruction
Bubble
Hazard
Instructions — edit and press Reset
Registers R0–R7
Memory (16 words)
Statistics
Cycles
0
Issued
0
Stalls
0
Flushes
0
Forwards
0
CPI
—
Event Log
CPU Pipeline Simulator
5-stage in-order pipeline with hazard detection & forwarding
The 5 Stages
IF Instruction Fetch → ID Decode & Register Read → EX Execute (ALU) → MEM Memory Access → WB Write Back
Hazards Simulated
Data Hazard (RAW) — instruction reads a register written by a recent instruction not yet in WB. With forwarding: bypass from EX or MEM output. Without: stall until WB commits.
Load-Use (Structural) — LOAD followed immediately by a dependent instruction always stalls 1 cycle (data isn't available until end of MEM, even with forwarding).
Control Hazard (Branch) — BEQ resolved in EX; always-not-taken prediction flushes IF+ID when branch is taken (1 cycle penalty).
Instruction Set
Instruction
Syntax
Semantics
ADD
ADD Rd, Rs1, Rs2
Rd = Rs1 + Rs2
SUB
SUB Rd, Rs1, Rs2
Rd = Rs1 - Rs2
MUL
MUL Rd, Rs1, Rs2
Rd = Rs1 × Rs2
LOAD
LOAD Rd, imm(Rs)
Rd = MEM[Rs + imm]
STORE
STORE Rs, imm(Rb)
MEM[Rb + imm] = Rs
BEQ
BEQ Rs1, Rs2, label
if Rs1 == Rs2: jump to label
NOP
NOP
No operation (1 cycle)
How to Use
Step — advance one clock cycle at a time
Auto — continuous simulation; pause to stop
Reset — restart from cycle 0 with current instructions
Edit the instruction list below the diagram (labels end with ":")
Toggle Forwarding to see the difference in stall count
Blue arrows on the diagram show active forwarding paths
Dashed boxes are pipeline bubbles (NOPs inserted by hardware)